The present invention generally relates to a semiconductor memory device having a sense amplifier for sensing and data of memory cell, and more specifically to a semiconductor memory device having a sense amplifier of which an amplifying method is sequentially turned by using a switch element controlled by a switch control signal and thus compensating for offset voltage between input and output terminals.
In general, a bit line sense amplifier senses and amplifies data loaded on bit line, and then provides the amplified data for data bus. Also a data bus sense amplifier senses and amplifies again the amplified data on data bus line and provides it for data output buffer. Here, the bit line sense amplifier employs a cross-coupled latch type amplifier.
The operation of the general bit line sense amplifier will be explained hereinafter.
First, the bit line is precharged to a precharge voltage (for example, a half of internal power supply voltage VDD). At that time, a pair of bit lines are equalized in order to eliminate voltage difference between a bit line connected to a selected memory cell and the other bit line.
A row decoder receives a row address from the outside of the semiconductor memory device and selects a word line corresponding to the row address. Then, cell transistors connected to the selected word line are turned on, causing a charge share between cell capacitance and bit line capacitance to be conductive. Thus, a potential difference is established between the bit line connected to the selected memory cell and the other bit line.
If sense amp control signals RTO and /S are enabled, i.e. the signal RTO goes up to a high level (e.g., VDD), and the signal /S falls down to a low level (e.g., VSS), the bit line sense amplifier achieves an operation for sensing and amplifying the potential difference between the bit line connected to the selected memory cell and the other bit line.
For instance, assuming that the data stored in the selected memory cell is at a low level, the potential of the bit line connected to the selected cell becomes lower than the precharge voltage. Since the other bit line retains the precharge voltage, the potential difference between two bit lines is resulted.
Thus, the bit line sense amplifier of cross-coupled latch type amplifier makes the bit line connected to the selected memory cell be at a low level VSS in response to the sense amp control signal /S, and the other bit line be at a high level VDD in response to the sense amp control signal RTO.
Next, if column decoder analyzes column address, and lets column control signal YI corresponding to the column address be enabled to a high level, the bit line sense amplifier activated by the column control signal YI transmits the amplified data onto the data bus.
However, when the conventional sense amplifier operates under a condition that a source voltage is lower than normal voltage, it cannot achieve the stable operation when sensing the data loaded on the bit line due to the offset voltage between the bit line and the sense amplifier. As a result, it takes a lot of time to sufficiently amplify the data on the bit line.
Under the condition of a low voltage, capacitance of the bit line becomes to be bigger than the cell. At the charge distribution the potential difference between the bit line connected to the selected memory cell and the other bit line decreases.
Thus, in case that the bit line sense amplifier senses a small voltage difference between the bit line connected to the selected memory cell and the other bit line, the operation thereof slows down due to the small voltage difference similar to the offset voltage. If the voltage difference is less than the offset voltage, the bit line sense amplifier may fail to sense the data, resulting in data error.
It is, therefore, an object of the present invention to improve sensing sensitivity and sufficiently amplify the data loaded on bit line, by changing an amplifying method of the sense amplifier.
It is another object of the present invention to achieve the stable operation by compensating for an offset voltage between input and output terminals of the sense amplifier in a semiconductor memory device.
In order to attain the above objects, according to an aspect of the present invention, there is provided a semiconductor memory device with a sense amplifier which is enabled in response to a sense amp control signal, and senses and amplifies data loaded on a bit line with using a predetermined power supply voltage. The sense amplifier includes switching means for changing a plurality of methods of amplifying the data. The amplifying method turns to a negative feedback differential amplifying method, a normal differential amplifying method, a positive feedback differential amplifying method, and a cross-coupled latch type amplifying method, in sequence.
According to another aspect of this invention, there is provided a method for driving a sense amplifier sensing and amplifying data loaded on bit line in a semiconductor memory device. The method comprises the steps of in sequence: turning an amplifying method of the sense amplifier into a negative feedback differential amplifying method for the purpose of compensating for an offset voltage between input and output terminals; turning an amplifying method of the sense amplifier into a normal differential amplifying method and amplifying the data loaded on the bit line; turning an amplifying method of the sense amplifier into a positive feedback differential amplifying method, compensating for an offset voltage between the input and output terminals, and re-amplifying the data amplified in the normal differential amplifying step; and turning an amplifying method of the sense amplifier into a cross-coupled latch method and then latching the data amplified in the positive feedback differential amplifying step.
The foregoing features and advantages of the invention will be more fully described in the accompanying drawings.